The present invention relates to a point memory graphic terminal provided with a system for recording or writing into an image memory image texture signals.
A point memory graphic terminal is shown in very general form in FIG. 1. It comprises a management microcomputer 10, a contro circuit 12, an image memory 14, a video signal generator 16 connected to the memory and finally a video display receiver 18. Circuit 12 comprises a memory address generator (GAM) and a plane selector (SP). Memory 14 is constituted by N memory planes.
FIG. 2 defines the structure of these elements and the various connections interconnecting them. It is also possible to see in a more detailed manner therein, the image memory 14 with its N memory planes 14.sub.1 . . . 14.sub.N (N being an integer at least equal to 1), each plane having a matrix system of points able to in each case store one bit. Each point is defined by an address. The N bits of N points with the same address in the different planes define a word of N bits, designated hereinafter by V. Memory 14 has an addressing input 14Ad common to the N planes and a control input 14C, which is also common to all the planes. It also has N validation inputs 14V.sub.1 . . . 14V.sub.N and N binary outputs 14S.sub.1 . . . 14S.sub.N.
The control circuit comprises a sequencer 20 and a graphic display processor 22. The sequencer has a clock output 20s.sub.1 and control outputs 20s.sub.2. The graphic display processor has an input 22e, a first group of outputs 22s.sub.1 associated with outputs 20s.sub.2 of the sequencer, said outputs supplying control signals SC defining an access cycle to the memory, a second group of outputs 22s.sub.2 supplying address signals SAd, a third group of outputs 22s.sub.3 supplying synchronization and clock signals SH for the generator 16. The control signals SC are applied by a first bus to the control input 14C of memory 14 and address signals SAd by a second bus to the addressing input 14Ad.
The control circuit 12 also has a circuit 24, which is connected to N gates 26.sub.1 . . . 26.sub.N, whereof the outputs are connected to the validation inputs 14V.sub.1 . . . 14V.sub.N of the memory. Circuit 24 controls the opening of gates 26.sub.1 . . . 26.sub.N for validating the memory planes in accordance with the signal supplied by output 22s.sub.1 of circuit 22.
All the means of circuit 12 fulfil the function of memory address generation (GAM) and plane selection (SP).
The video signal generator 16 has N binary inputs 16e.sub.1 . . . 16e.sub.N connected to N binary outputs of the image memory 14, a synchronization input 16E connected to the third group of outputs 22s.sub.3 of the graphic display processor 22 and a clock input 16H connected to the clock output 20s.sub.1 of sequencer 20. Generator 16 also has an output 16s supplying video signals (R, V, B) and synchronization signals (S).
A graphic terminal of this type serves to produce images from the information which it receives or processes. These images are designed and stored point by point in memory 14, which for this reason is called an "image memory". The management of such a graphic terminal is ensured by microcomputer 10, which converses with the outside (in practice with a host computer, another terminal, a keyboard, a graphic board, etc) and transforms requests for creating images into appropriate signals, which are supplied to its output 10s.sub.1 and addressed to the control circuit 12. The latter is designed in such a way that the values corresponding to each of the points constituting the graphic symbol to be displayed are written into the image memory. These values translate the appearance of each of the points in the way in which they are to appear on the screen. It can be a question of the luminance, primary colours or any other magnitude making it possible to restore one or other of these characteristics.
Two operations must be simultaneously performed for recording or writing a graphic symbol into the image memory, namely a definition of the skeleton of the graphic symbol, which is obtained by the definition of a group of points and an evaluation, for each of these points of the skeleton, of the value V which is to be represented in the image memory. The first operation is carried out by the memory address generator GAM, which generates addresses, or in other words coordinates of points, whilst the second operation is performed by the plane selector SP. The value V is one of the 2.sup.N possible values and is translated by a word of N bits formed by bits equal to 0 or to 1. Each "1" with a given rank in the word is stored in the memory plane of the same rank at the address defined by the address generator. Thus, when circuit 12 consists of a graphic symbol, it simultaneously determines the coordinates x, y of the points forming this graphic symbol and the planes of the memory which it has to validate.
The function of the video generator 16 is to convert the signal read into the image memory into a signal able to control a display means, such as a video receiver. Typically, this signal is of the type encountered in television. It should be noted, that in reading, the video generator 16 has permanent access to the image memory.
The assembly formed by circuit 12, image memory 14 and generator 16 constitutes what is called an automatic visual display means. In a first generation, the design of such means essentially was based on the software used for defining the operation necessary for the display of characters, points, vectors, circular arcs, spots, etc. The disadvantage of such equipment is that they lead to a relatively long performance time. Therefore, certain functions particularly connected to the image memory and the video generator, have undergone certain improvements of an equipment nature in order to speed up the processing of the trace, plot or outline generator.
A second generation of display means appeared with the development of specialized integrated circuits relating to the management of point image memories (e.g. EFCIS 9365 or NEC 7220 circuits). In general, these circuits combine the functions of the overall management of the memory, both for the writing trace generator and for the reading video generator in the management of the actual memory (dynamic memory refreshing). They also ensure the functions of the structuring of the video signal (synchronization, clearing period) and certain trace functions (characters, segments, circular arcs, etc).
However, such circuits only function with a single memory plane. They are characterized mainly by a high speed of effecting the traces, but have a less fine control of the graphic symbols obtained.
Among the terminals of the first generation, reference can be made to the terminal especially designed for telerecording or alphageometric videographics, forming the object of French patent application No. 2,465,281 entitled "Device for the digital transmission and display of graphic symbols and/or characters on a screen". In such a terminal, the writing accesses of the image memory are under the control of the software, which integrally determines each point to be written and its value. The aforementioned GAM and SP functions are then obtained by instruction programmes. With such a terminal, it is possible to perform a so-called zone filling process, in order to cover part of the image by hatching, or to give it a particular shade or tint.
The various functions fulfilled by these equipments permit a considerable flexibility with regards to the formation of the images but, as they require a considerable processing time, these functions are in practice limited to simple processing operations, i.e. uniform colour filling, elementary hatching, etc.
In the terminals of the second generation, the software plays a smaller part than the hardware. The integrated circuits used carry out a high level management of the image memory. For example, the graphic display processor EF 9365 developed by EFCIS directly generates at high speed in the image memory characters or vectors. However, in this case, the appearance of the displayed points is not as finely controlled, because this type of circuit is unaware of the notion of memory planes.
Thus, the known terminals are unable to reconcile the speed of obtaining an image and the fine detailed resolution thereof. The solutions using circuits specialized in the management of image memories favour the first parameter, but penalize the second. Conversely, the necessary image resolution can be obtained by software, but then the processing time becomes too long.